1. Field of the Invention
The invention relates to an output circuit of a memory and a method thereof; and more particularly, to an output circuit and method thereof for a static random access memory (SRAM).
2. Description of the Related Art
Most memory data is in the form of binary bits and each bit is stored in a memory cell as 0 or 1. The memory cells are arranged in a rectangular matrix and form the principle part of the memory. Before writing data to a specific memory cell, the memory cell is selected by an address latch circuit, and the bit is then written into the memory cell. Before data is read from a specific memory cell, the memory cell is selected by the address latch circuit, and the bit stored in the memory cell is then output in the form of current or voltage through the output circuit. Because the current or voltage output from the memory cell is very weak, it is amplified by a current or voltage amplifier to the level of standard digital signal strength.
Static random access memory (SRAM) remains data therein as long as power is supplied, unlike dynamic random access memory (DRAM), which requires periodic refreshing, with access time of a SRAM less than that of a DRAM. Thus, SRAM is often used as cache memory, or as part of the random access memory of a digital to analog converter in a graphics card.
The performance a SRAM is determined by the access time for determining the operating speed of the memory and a controller or a central processing unit as a whole. Because there are thousands of SRAM cells connected to a single output circuit, a great number of parasitic capacitors are generated. Since the driving ability of a SRAM cell is weak, the latency caused by the parasitic capacitors is a factor affecting the access time of a SRAM. Thus, an output circuit capable of reducing the SRAM access time to increase the performance of the SRAM is desirable.